This invention relates generally to the suppression of electrical noise propagated in the substrate of a semiconductor integrated circuit device, particularly for the case of a highly integrated device.
Semiconductor integrated circuit devices, particularly those having a high level of integration as in the case of the so-called systems-on-a-chip, are known to have both noise-generating circuit elements, as well as noise-sensitive circuit elements, on the same die. The noise-generating elements are typically digital circuits involving high-speed switching operations, such as DSP (Digital Signal Processing) or microprocessor core circuits, RAM (Random Access Memory), ROM (Read-Only Memory), line/bus drivers, I/O (Input/Output) drivers, etc. The noise-sensitive elements are typically analog circuits, such as A-D (Analog-to-Digital) or D-A (Digital-to-Analog) converters, filters, operational amplifiers, comparators, bias circuits, etc. Noise signals generated by the noisy elements propagate in the substrate to the noise-sensitive circuits as interference. The substrate noise interference level is a very important determinant of the degree of integration that is possible on a single die. An increase of the spacing between the noise generating elements and the noise sensitive elements is an obvious method for reduction of the noise interference level, but the degree of integration possible on a chip is thereby substantially reduced. One trend in semiconductor technology is toward smaller spaces between circuit elements. Another important trend is the integration of system functions into integrated circuits with the systems being integrated having widely differing characteristics of noise sensitivity and noise generation. Therefore the reduction of substrate noise in highly integrated semiconductor devices is of paramount importance.
Often, the methods and apparatuses used for substrate noise reduction require expensive changes to conventional semiconductor manufacturing processes, such as grooves in the semiconductor device as in U.S. Pat. No. 4,470,062, and electroconductive walls as in U.S. Pat. No. 5,196,920. In U.S. Pat. No. 5,475,255, Joarder et al. disclose a noise reduction technique that utilizes one or two guard rings that partially surround or completely surround each noise-generating circuit element or each noise-sensitive circuit element. Each guard ring and each circuit element is assigned separate connections to a common electrical ground external to the device. The approach is impractical for highly integrated devices because the number of circuit elements and guard rings can be very large and for the invention of Joarder et al. the number of device pins required for external ground connection increases linearly with the number of circuit elements and guard rings.
Previous patents have disclosed guard bands surrounding noise-generating or noise-sensitive regions (NG/NS regions) circuit portions having metal-diffusion contacts connecting to metal interconnection lines that are dedicated to particular package pins. Each of the separate noise-generating or noise-sensitive circuit portions are separately allocated separate package pins. The number of allocated package pins thus grows as more independent circuit portions are integrated onto a single IC chip. This soon becomes impractical for large, multifunctional highly integrated systems.
Accordingly, the present invention provides for an apparatus and method for effective substrate noise reduction in highly integrated semiconductor devices without need for a substantial overhead in the number of device input/output pins required to support the noise suppression function. Further, the noise suppression apparatus and method of the invention employ inexpensive conventional semiconductor manufacturing processes. In the layout on the substrate, the circuits are partitioned into a plurality [Ng] of noise-generating [NG] regions and a plurality [Ms] of noise-sensitive [Sm] regions, where each noisy region contains a plurality of noise-generating circuit blocks and each noise-sensitive region contains a plurality of noise-sensitive circuit blocks. For each region an independent metal conductor power distribution mesh and an independent metal conductor ground distribution mesh is formed around the perimeter of the respective region and serves as common power supply and ground reference, respectively, for all the circuit blocks of the respective region. Each Gm and Sm region is embedded with a respective mesh of P+ noise guard bands and a respective mesh of N+ noise guard bands. The N+ mesh and the power distribution mesh are configured so that the power metal conductor distribution mesh overlies a substantial portion of the N+ guard band mesh. The power metal conductor distribution mesh is positioned above the N+ guard band mesh so that they may be easily connected through a plurality of spaced apart N+-to-power metal contact openings [also called vias] provided in the insulating layer (or layers) between them. The N+-to-power metal contact openings permit the power metal conductor to make solid electrically conducting contact to the N+ guard band diffusion beneath the corresponding vias between meshes.
Similarly, the P+ guard band mesh has a solid electrically conducting tie to the ground conductor metal distribution mesh through a respective plurality of spaced apart P+-to-ground metal vias positioned between the P+ and ground metal mesh above it in its respective region. The P+ mesh together with the ground mesh tied to it, and the N+ mesh together with the power mesh tied to it, are configured in each respective region such that each circuit block within a region is separated from adjacent blocks of the same region and separated from adjacent blocks of adjacent regions by both N+ and P+ guard bands. More specifically, Sm blocks are separated from Sm blocks and from Gm blocks by both N+ and P+ guard bands, and Gm blocks are separated from Sm blocks and from Gm blocks by both N+ and P+ guard bands. In this way each noise-sensitive circuit block is isolated from noisy circuit blocks by the guard bands.
One of the advantages of the present invention is that this invention leverages a feature that is becoming more common in chip layout of large integrated circuits. That is, metal conductor ground meshes and metal conductor power supply meshes are being used to distribute power and ground to different circuit regions merely for the purpose of maintaining uniform voltages over large, widely separated circuit regions. Thus the chip area that is already used by the power-ground distribution meshes merely for the uniform distribution of voltage, is advantageously used to contain the isolating guard bands at no additional penalty in chip area.
Along any lateral substrate path between a noise-generating bock and a noise-sensitive block, the alternating N+ and P+ guard bands substantially increase the impedance of the lateral paths by xe2x80x9cpinching offxe2x80x9d the thickness of the lateral path by the protrusion of their respective diffusion depths into the substrate. The P+ and N+ guard bands also act as effective sinks for noise generated in other regions and transmitted laterally along the substrate. Because the guard meshes are tied to the already existing power/ground distribution meshes for the regions, no significant overhead in additional external device pins is incurred to support the substrate noise suppression function. For a noisy region, the conductor metal connected guard meshes of each circuit block and each circuit region substantially confine noise generated by each noisy block to the local area of the block. For a noise-sensitive region, the guard meshes of the region substantially isolate each noise sensitive block from all residual externally generated noise from impinging on the block by transmission through the substrate.
The invention is described in its preferred embodiment as a CMOS device fabricated in an N-well process with a P-type substrate. The described method of the invention will be seen to extend in obvious ways to N-substrate CMOS, Triple-well CMOS, BiCMOS, and bipolar semiconductor technologies.
Another advantage of the present invention is the limited number of additional package pins required for effective noise isolation between Sm and Gm regions and between adjacent Smxe2x80x94Sm blocks or adjacent Gmxe2x80x94Gm blocks is much less than the number of pins required by previous isolation methods. In contrast to prior methods, the present invention provides that sufficient noise isolation can be attained by having respective ground and power metal conductor meshes of individual Sm regions and individual Gm regions electrically connected on the IC chip to corresponding metal conductor meshes of one or more other corresponding individual Sm regions and individual Gm regions, rather than on the printed circuit board to which the IC chip is mounted. Such connections may be made at intermediate points of the IC chip circuit layout, or at a particular single chip-bonding pad connected to a particular single chip package pin. This is in contrast to prior methods which necessitated each noise isolated region be connected through its own, separate package pin before making a common connection to a metal conductor on the printed circuit board on which the IC was mounted, in order to achieve sufficient noise isolation between noisy and noise-sensitive regions or blocks.